1. Field of the Invention
This invention relates generally to the method and system of testing the integrated circuits (ICs), electronic components and systems. More particularly, this invention relates to an simplified system configuration and method for testing the integrated circuits, electronic components and systems by employing a computer and taping signal from the data path between the CPU and the memory or other peripheral storage to significantly reduce the cost by eliminating the requirement to custom build a high-speed controller specifically for controlling the testing processes as that required in the conventional testing systems.
2. Description of the Prior Art
As the integrated circuits (ICs), electronic components and systems become more complicate with higher level of integration and increasingly faster operational speed, the traditional techniques of test system architecture configurations and methods are challenged by many technical difficulties. One of the major difficulties is the requirement of a high-speed controller (HSC) to control and manage the data transfer and test data verifications and to coordinate other necessary test related processes. Due the performance requirements of speed and data handling capabilities, this high-speed controller is quite complicate. The whole system is build by assembling many different kinds of high-performance integrated circuits (ICs) according to the designs and system architectures generated by very sophisticate design teams. The high-speed controller thus becomes an expensive item that leads to a very high production cost and development engineering cost of the testing system.
FIG. 1 is a functional block diagrams for showing the system configuration of a conventional test high-speed teat system. The conventional test system 10 is configured for testing a device under test 15 using a test head 20 receiving data from formatter and timing unit (FTM) 25. The test results are sent to a response unit (RP) 30 that includes an exclusive OR circuit for comparing the test results from the test head 20 and the test patterns with variable timing strobes sent from the FTM 25. In the conventional architecture, the high speed testing system includes a background computer BGCMP 50 for loading data to and from a local high speed memory LM 35 and performs other functions such as user interface and other background tasks. The testing system 10 further includes a high speed controller 40 to control the high speed local memory 35 to send the test patterns to FTM and RP.
Due to the rapid development of very large-scale integrated circuit (VLSI) and system on chip (S.O.C) technology, the extreme circuit complexity of state of art VLSI and S.O.C. has required high speed processing capability of the high speed controller and a high speed large LM. The efforts spent in designing and producing a high speed controller and a high speed large local memory (LM) become a major cost in designing and building a conventional high speed testing system as that illustrated in FIG. 1.
Therefore, there is still a demand in the art of IC testing for a new and simplified system configuration to reduce the design and production cost of a high-speed testing system.